1. Field of the Invention
Embodiments of the present invention relate to a duty cycle correction circuit, and more particularly, to a duty cycle correction circuit adjusting current characteristic using a digital duty error detector and a method thereof.
2. Description of the Related Art
For systems that use a multi-phase clock signal, e.g., Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), an analog to digital converter (ADC), etc., an analog duty cycle correction circuit may be used to maintain a constant, e.g., 50%, duty cycle (or duty rate).
Since the analog duty cycle correction circuit stores information on duty error, e.g., deviation from a desired duty cycle, in a capacitor, information on the duty error may be damaged by a leakage current of the capacitor when the analog duty cycle correction circuit is powered off in a power down mode to reduce power consumption. When the analog duty cycle correction circuit is driven into an active mode from a power down mode, settling time of the analog duty cycle correction circuit may be increased.
FIG. 1 illustrates a block diagram of a conventional duty cycle correction circuit. FIG. 2 illustrates a detailed circuit diagram of a duty cycle correction circuit illustrated in FIG. 1. Referring to FIGS. 1 and 2, a duty cycle correction circuit 10 may include a corrector 12 correcting a duty error and a detector 14 detecting a duty error. An analog offset voltage generated in the detector 14 may be stored in each capacitor 16 and 18, and an offset voltage stored in each capacitor 16 and 18 may correct duty errors of clock signals Ci and Cib by generating a current difference of a transistor for a correction.
Current gain of the detector 14 for each capacitor 16 and 18 in the duty cycle correction circuit 10 is an important design factor. Current gain may be increased to lessen settling time, but this increase may provoke an error for duty cycle correction after settling time. Thus, there is a trade-off relation between settling time and accuracy of duty error correction.
Because accuracy and power consumption for duty cycle are very important design specifications in high speed devices, i.e., device that use a multi-phase clock signal, when an analog duty cycle correction circuit is turned off in a power down mode, information is stored in a capacitor having a much bigger capacity than current gain. Accordingly, when restored to active mode, a conventional analog duty cycle correction circuit has long settling time before a duty cycle may be corrected to the desired, e.g., 50%, duty cycle.